Translation Lookaside Buffer - definizione. Che cos'è Translation Lookaside Buffer
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Cosa (chi) è Translation Lookaside Buffer - definizione


Translation lookaside buffer         
  • location=United States of America}}</ref> shows the working of a translation lookaside buffer. For simplicity, the page-fault routine is not mentioned.
  • location=United States of America}}</ref>
MEMORY CACHE THAT IS USED TO REDUCE THE TIME TAKEN TO ACCESS A USER MEMORY LOCATION; PART OF THE CHIP’S MEMORY-MANAGEMENT UNIT
Translation-Lookaside Buffer; Translation-lookaside buffer; Translation Lookaside Buffer; Address Translation Registers; ITLB; DTLB; TLB flush; Process context identifiers; Process-context identifier; Process context identifier; Address space number; Translation look-aside buffer; Speculative translation lookaside buffer; Secondary translation lookaside buffer
A translation lookaside buffer (TLB) is a memory cache that stores the recent translations of virtual memory to physical memory. It is used to reduce the time taken to access a user memory location.
Translation Look-aside Buffer         
  • location=United States of America}}</ref> shows the working of a translation lookaside buffer. For simplicity, the page-fault routine is not mentioned.
  • location=United States of America}}</ref>
MEMORY CACHE THAT IS USED TO REDUCE THE TIME TAKEN TO ACCESS A USER MEMORY LOCATION; PART OF THE CHIP’S MEMORY-MANAGEMENT UNIT
Translation-Lookaside Buffer; Translation-lookaside buffer; Translation Lookaside Buffer; Address Translation Registers; ITLB; DTLB; TLB flush; Process context identifiers; Process-context identifier; Process context identifier; Address space number; Translation look-aside buffer; Speculative translation lookaside buffer; Secondary translation lookaside buffer
<storage, architecture> (TLB) A table used in a {virtual memory} system, that lists the physical address page number associated with each virtual address page number. A TLB is used in conjunction with a cache whose tags are based on virtual addresses. The virtual address is presented simultaneously to the TLB and to the cache so that cache access and the virtual-to-physical address translation can proceed in parallel (the translation is done "on the side"). If the requested address is not cached then the physical address is used to locate the data in main memory. The alternative would be to place the translation table between the cache and main memory so that it will only be activated once there was a cache miss. (1995-01-30)
DTLB         
  • location=United States of America}}</ref> shows the working of a translation lookaside buffer. For simplicity, the page-fault routine is not mentioned.
  • location=United States of America}}</ref>
MEMORY CACHE THAT IS USED TO REDUCE THE TIME TAKEN TO ACCESS A USER MEMORY LOCATION; PART OF THE CHIP’S MEMORY-MANAGEMENT UNIT
Translation-Lookaside Buffer; Translation-lookaside buffer; Translation Lookaside Buffer; Address Translation Registers; ITLB; DTLB; TLB flush; Process context identifiers; Process-context identifier; Process context identifier; Address space number; Translation look-aside buffer; Speculative translation lookaside buffer; Secondary translation lookaside buffer
Dual Translation Lookaside Buffer (Reference: CPU)